--
-- VHDL Architecture Fietscomputer_lib.gen_multiplier.combi
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp7985)
--          at - 16:49:17  7-07-2010
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY fc_63_to_49 IS

  PORT( 
  input   : IN     STD_LOGIC_VECTOR(63 DOWNTO 0);
  uit   : OUT     STD_LOGIC_VECTOR(49 DOWNTO 0)
  );
  
  
END fc_63_to_49 ;


ARCHITECTURE combi OF fc_63_to_49 IS




BEGIN
  
  
  uit <= input(49 DOWNTO 0);
    
  
   
    
  END ARCHITECTURE combi;
  
  
  
  
  